1. Field of the Invention
An embodiment of the present invention relates to microelectronic device fabrication. In particular, an embodiment of the present invention relates to methods for forming copper interconnects.
2. State of the Art
The microelectronic device industry continues to see tremendous advances in technologies that permit increased integrated circuit density and complexity, and equally dramatic decreases in package sizes. Present semiconductor technology now permits single-chip microprocessors with many millions of transistors, operating at speeds of tens (or even hundreds) of MIPS (millions of instructions per second), to be packaged in relatively small, air-cooled microelectronic device packages. These transistors are generally connected to one another or to devices external to the microelectronic device by conductive traces and contacts (hereinafter referred to collectively as “interconnects”) through which electronic signals are sent and/or received.
A typical process of forming interconnects includes patterning a photoresist material on an interlayer dielectric material and plasma etching the interlayer dielectric material through the photoresist material pattern to form a hole and/or a trench (hereinafter referred to collectively as an “opening”) extending into the interlayer dielectric material. The photoresist material (which may also include hard mask and antireflective coating layers) is then removed (typically by an oxygen or hydrogen plasma followed by wet cleans or all-wet cleans) and a barrier layer may be deposited within the opening to prevent conductive material (particularly copper and copper-containing alloys), which will be subsequently deposited into the opening, from migrating into interlayer dielectric material. The migration of the conductive material can adversely affect the quality of microelectronic device, such as leakage current and reliability of the interconnects. Thus, a barrier layer is deposited onto a dielectric layer to line the opening. In addition to lining the opening, a separate barrier layer is deposited across a top surface of the dielectric layer.
A seed material may then be deposited on the barrier layer, followed by performing a conventional electroplating process to form a conductive material layer. Like the barrier layer, excess conductive material layer may form on barrier layer covering the dielectric layer. The resulting structure is planarized, usually by a technique called chemical mechanical polish (CMP), which removes a portion of the conductive material layer and the barrier layer that are not within the opening from the surface of the dielectric material, to form the interconnect structure, which is electrically segregated from other such interconnect structures.
Although this is an effective way of forming an interconnect, as the size of the integrated circuitry decreases, the interlayer dielectric material becomes less able to prevent cross-talk between adjacent interconnects, as will be understood to those skilled in the art. Thus, there has been a movement to completely remove the interlayer dielectric from between the interconnects, thereby allowing an air gap to act as the dielectric (i.e., air has a dielectric constant of 1.0). However, the removal of the interlayer dielectric material has issues. With carbon-based interlayer dielectrics, removal thereof is achieved by a reducing plasma etch chemistry. However, such a removal process can result in interconnect electrical damage and/or corner rounding of the interconnects due to the ion bombardment during the process. With silicon-based interlayer dielectrics, removal thereof is achieved by a fluorine-based wet chemistry, which can potentially damage the interconnect and any capping layer (such as copper and electroless cobalt, respectively) as it is not particularly selectively to such materials. Silicon-based interlayer dielectrics may also be removed with a CFx plasma chemistry, which can result in corner rounding and/or sputtering of the interconnect material (such as copper), as will be understood by those skilled in the art.
Therefore, it would be advantageous to develop techniques to form an interconnect having an air gap dielectric, which reduces or substantially eliminates the potential of damage to the interconnect structure.